1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a transistor and a method of forming a transistor using pressurized nitrogen during a post implant anneal cycle to minimize migration of the implant species into critical areas.
2. Description of the Relevant Art
Fabrication of a metal-oxide semiconductor ("MOS") transistor is well known. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas on the semiconductor substrate by various isolation structures formed upon and within the substrate. Isolation structures come in many forms. For example, the isolation structures can be formed by etching trenches into the substrate and then filling the trenches with a dielectric fill material. Isolation structures may also be formed by locally oxidizing the silicon substrate using the well recognized LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in, for example, an oxidation furnace or a rapid thermal anneal ("RTA") chamber. A gate conductor material is then deposited across the entire dielectric-covered substrate. The gate conductor material is preferably polycrystalline silicon, or polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the "develop" stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
An n-channel transistor, or NMOS transistor, must in most instances be fabricated different from a p-channel transistor, or PMOS transistor. NMOS transistors employ n-type dopants on opposite sides of the NMOS gate conductor, whereas PMOS transistors employ p-type dopants on opposite sides of the PMOS transistor gate conductor. The regions of the substrate which receive dopants on opposite sides of the gate conductor are generally referred to as junction regions, and the distance between junction regions is typically referred to as the physical channel length. After implantation and subsequent diffusion of the junction regions, the distance between the junction regions become less than the physical channel length and is often referred to as the effective channel length ("Leff"). In high density designs, not only does the physical channel length become small, so too must the Leff. As Leff decreases below approximately 1.0 .mu.m, for example, a problem known as short channel effects ("SCE") becomes predominant.
A problem related to SCE, and the subthreshold currents associated therewith, but altogether different is the problem of hot-carrier effects ("HCE"). HCE is a phenomenon by which hot-carriers ("holes and electrons") arrive at or near an electric field gradient. The electric field gradient, often referred to as the maximum electric field ("Em"), occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent to the channel. The electric field at the drain causes primarily electrons in the channel to gain kinetic energy and become "hot" . These hot electrons traveling to the drain lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors.
Unless modifications are made to the fabrication sequence, problems resulting from HCE will remain. To minimize these problems, a mechanism must be derived that disperses and thereby reduces Em. That mechanism is often referred to as the double-diffused drain ("DDD") and lightly doped drain ("LDD") techniques. The purpose behind using DDDs and LDDs structures is to absorb some of the potential into the drain and away from the drain/channel interface. The popularity of DDD structures has given way to LDD structures since DDD causes unacceptably deep junctions and deleterious junction capacitance.
A conventional LDD structure is one whereby a light concentration of dopant is self-aligned to the edge of the gate conductor. The light-dopant concentration is then followed by a heavier-dopant concentration which is self-aligned to a spacer formed on the sidewalls of the gate conductor. The purpose of the first implant dose is to produce a lightly doped section within the junction at the gate edge, near the channel. The second implant dose within the junction is spaced from the channel a distance dictated by the thickness of the sidewall spacer. Resulting from the first and second implants, a dopant gradient occurs across the junction from the source/drain area of the junction to the LDD area adjacent the channel.
The LDD implant solves to some extent the HCE problem, but does so at a cost. Dispersion of Em requires that the LDD implant area be sufficiently large near the critical drain-side of the channel. Due to the symmetrical nature of the LDD implant, the large LDD implant area at the drain also occurs near the source-side of the channel. Thus, the LDD implant adds significant parasitic resistance and capacitance to the source-drain path of the ensuing transistor. The added resistance/capacitance is compounded to some extent by migrating LDD dopants during subsequent heat cycles. While heating is necessary to repair implant damage and activate the dopants within the crystalline lattice, heating unfortunately spreads the LDD area toward critical channel and overlying gate dielectric regions. Heating used to repair implant is often referred to as "anneal" . Annealing the crystalline substrate is necessary post implant. Depending upon the amount of implant damage, the anneal temperature can vary. For example, small point defects, or clusters of irregularly arranged lattice areas can be re-oriented to their proper positions using a relatively low temperature anneal. However, if the localized defect areas become amorphized, or the amorphized region is continuous throughout the implant layer, then a much higher anneal temperature is needed. Typically, the anneal temperature needed to repair amorphized or heavy primary crystalline damage ranges between 850.degree. C. to 1050.degree. C.
As a byproduct to the anneal cycle, dopants within the LDD segregate and migrate in a vertical as well as horizontal direction. Diffusion causes enlargement of the LDD area, leading to enhanced parasitic problems. Further, diffusion of LDD dopants into the channel causes enhanced SCE problems. While it is necessary to anneal implant damage from the crystalline lattice, it would be desirable to do so with minimal migration of the implanted dopant. More specifically, a process must be derived which can carefully control implants placed close to critical areas--i.e., control of the LDD dopants placed closer to the channel than other implant areas is needed. Control implies placing limits on the diffusion length of the LDD dopants toward the critical areas. The improved process must be one which can minimize HCE and the problems of hot carriers injected from the drain-side LDD into the gate oxide.